The invention relates to a control circuit for the data path of an S-DRAM. RAM modules are standard memory modules for main memory. D-RAM memories comprise large scale integrated transistors and capacitors. In order to maintain the information, the memory content has to be continually refreshed in this case (refresh). A synchronous D-RAM (S-DRAM) permits the memory access without additional waiting cycles. In this case, the data transfer between the S-DRAM and an external data bus is effected synchronously with the external clock signal.
FIG. 1 shows an S-DRAM memory module according to the prior art. The S-DRAM memory module is connected to an external control bus, to an external address bus and to an external data bus. Via command PADS, the control commands present on the external control bus are read in by an integrated command receiver and the reception signals are applied, after having undergone signal amplification, to a command decoder. The command decoder decodes the applied control commands, which have a width of 4 bits, for example, to form internal control commands, such as, for instance, write (WR) and read (RD). The S-DRAM comprises a state machine or a sequence controller which controls the internal sequences in a manner dependent on the decoded internal control commands. The sequence controller is clocked by a clock signal. For this purpose, an external clock signal CLKext is applied to the S-DRAM and signal-amplified by an integrated clock signal receiver. The amplified clock signal is distributed by a clock tree in a tree-like manner in the integrated S-DRAM and passes via an internal clock line to a sequence controller. The external clock signal is furthermore applied to a delay locked loop DLL. The delay locked loop DLL effects a negative phase shift of the external clock signal CLK that is present. The internal DLL clock signal leads the external clock signal in order that the data are present synchronously with the external clock signal at the data pads. The output signal driver OCD (off chip driver) of a data path, said output signal driver being integrated in the S-DRAM, is clocked with the DLL clock signal DLLCLK. Connected downstream of the delay locked loop DLL is a propagation time element which forms an internal clock signal (VE-CLK) which is simulated identically to the external clock signal, i.e. VE-CLK is completely synchronous with CLKext. The propagation time element in this respect compensates for the negative phase shift of the delay locked loop DLL.
The internal sequence controller generates control signals for the internal operating sequence of the S-DRAM in a manner dependent on the decoded commands. The sequence controller generates an RAS signal (row address strobe) for driving a row address latch and a CAS signal (column address select) for driving a column address latch. The row address latch and the column address latch are connected to an address signal receiver of the S-DRAM via an internal address bus. The S-DRAM receives an external address via the external address bus at the address PADS, the address signals present being signal-amplified by an address receiver. In order to save terminals, the address is input in two steps in DRAM memories. In a first step, the lower address bits are loaded with the RAS signal into the row address latch. In a second step, the more-significant address bits are loaded with the CAS signal into the column address latch. The address bits are applied to a row and column decoder, respectively, for access to a memory cell within the matrix-type memory cell array. The row address latch and the column address latch and also the row decoder and column decoder together form an address signal decoder. For the refresh of the memory cells, the memory cell array receives a refresh control signal from the sequence controller. A refresh counter, which receives an enable signal from the sequence controller, successively generates all existing row addresses, which are then applied to the address bus. The sequence controller generates an RAS control signal for this purpose. Through the activation of a word line, all the memory cells connected to it are refreshed.
The memory cell array is furthermore connected to read/write amplifiers. The number of read/write amplifiers depends on the memory architecture, the word width and the prefetch. Given prefetch 4 with a word width of 32, by way of example, 128 read/write amplifiers are in operation simultaneously. If four independent memory banks are provided, for example, a total of 512 read/write amplifiers are integrated on the memory chip.
Via the read/write amplifiers, a data bit is in each case written to an addressed memory cell or read from it. The read/write amplifiers are connected to an internal data path of the S-DRAM via an internal data bus. Via the data path, the data present in the external data bus are written to the S-DRAM synchronously and output from the S-DRAM synchronously. The data path is connected to the data PADS of the S-DRAM.
For reading in the data, the data path acquires a data receiver for receiving the data that are present externally. An internal driver circuit for the data to be written (WR driver) carries out a signal amplification of the received data and outputs the read-in data to the read/write amplifiers via the internal bus. The driver circuit WR driver is driven by a write latency generator which is clocked by the internal clock signal VE-CLK. For its part, the write latency generator is connected to a decoder.
For synchronous outputting of data, the data path contains a data FIFO register, downstream of which an output data driver circuit (OCD driver) is connected. The FIFO register is driven by the read/write amplifier by means of an input pointer and by a read latency generator by means of an output pointer or a time-delayed data enable signal. The read latency generator is likewise connected to a decoder.
The two decoders for the read latency generator and the write latency generator are connected via internal control lines to a mode register in which the data for controlling the operating modes within the S-DRAM are stored. The mode register can be initialized by a mode register set command via the internal address bus. The mode register is initialized after the switch-on. Before external control commands are applied to the S-DRAM, the mode register is initialized. The mode register contains control data for the CAS latency, for test modes and for a DLL reset.
The sequence controller generates, in a manner dependent on the external control commands, an internal write command PAW for activating the write latency generator and an internal read command PAR for activating the read latency generator.
FIG. 2 shows a timing diagram for elucidating the method of operation of a conventional S-DRAM. An external clock signal CLK-external is present at the S-DRAM. The state machine or sequence controller generates an internal command signal in a manner dependent on the decoded read command RD. The read command is applied relative to a rising signal edge of the external clock signal CLKext. The clock signal is received and distributed. With the internal clock signal CLKint, the command is accepted and subsequently decoded. The sequence controller generates an internal read command control signal PARint, for example.
The internal control signal PARint is generated with a certain signal delay, namely an out-decoding time xcex94tDEK. This out-decoding time comprises a signal delay on account of the clock signal receiver, on account of the clock signal line tree (clock tree) and on account of signal delays within the sequence controller.
tDEK=tCLKRECEIVER+tCLKTREE+tLatch+tCMDDecode+tPARGENERATION
The generated internal read signal PARint is applied to the read/write amplifiers with a short signal delay and said amplifiers output the data to be read out to the internal data bus. With a further time delay xcex94tFIFO the data pass from the internal data bus via the FIFO register within the data path to the input of the OCD driver. The OCD driver or data output driver outputs the data to the data PADS of the S-DRAM with a further signal delay xcex94tOCD. Between the edge of the external clock signal upon which the decoded internal read command RD is applied and the outputting of data via the data PADS, there is a delay time xcex94T.
FIG. 3a shows a read latency generator and FIG. 3b shows a write latency generator according to the prior art.
As can be discerned from FIG. 3a, in order to achieve a read latency or CAS latency of CAS=6, the synchronized internal read signal PARxe2x80x3int is applied to the chain of timing elements within the read latency generator and delayed with a delay time corresponding to four times the clock cycle time xcex94tcycle. In order to achieve a CAS latency of 5, the synchronized internal read signal merely passes through 3 timing elements, and in order to achieve a CAS latency of 4, the synchronized internal read signal merely passes through 2 timing elements. Accordingly, on an internal multiplexer of the read latency generator, three inputs are provided which are connected to outputs of timing elements within the chain. The decoder decodes the desired CAS latency stored in digital form in the mode register and drives the multiplexer via a control line. If a CAS latency of 4, for example, is stored in the mode register, the decoder switches through the third input of the multiplexer to the output control line. On the output side, the multiplexer is connected to the FIFO register and outputs a time-delayed enable signal to the FIFO register.
FIG. 4a shows a timing diagram for elucidating the function of a read latency generator or latency counter according to the prior art as is illustrated in FIG. 3a. The example illustrated in FIG. 4a shows the sequence given a stored CAS latency of 4. The decoder identifies the CAS latency of 4 and switches over the multiplexer, so that a time delay is effected by two clocked timing elements. Since the timing elements in the read latency generator are clocked by the internal clock signal DLL-CLK, a time-delayed data enabling is effected after the third rising edge of the DLL-CLK clock signal.
However, the internal read command signal applied to the read latency generator passes to the latency generator only in a time-delayed manner with a time delay xcex94tDEK. As the clock frequency of the external clock signal increases, the cycle time tcycle of the clock signal decreases. At a clock rate of 500 MHz, the cycle time tcycle only 2 ns and is in the region of signal propagation times on the chip. Since the time delay xcex94tDEK is constant, the situation arises, in the case of a clock signal at a very high frequency, in which the signal time delay xcex94tDEK becomes greater than the cycle time tcycle. In this case, the synchronization of the internal read signal PARint to PARintxe2x80x2 takes place incorrectly one clock edge of the VECLK clock too late, that is to say with the VECLK edge 2 instead of with the VECLK edge.
A second error mechanism independent thereof relates to the offset between the VECLK and the DLLCLK. If the propagation time of the OCD and the propagation time of the FIFO become greater than tcycle, the temporal offset between VELCK [sic] and DLLCLK also becomes greater than 1tcycle.
In this case, the synchronization of the internal read signal PARxe2x80x2int to PARxe2x80x3int takes place incorrectly one clock edge of the DLL clock signal DLL-CLK later, i.e. with the signal edge 2, instead of correctly with the signal edge 1.
Consequently, as soon as one of the two error mechanisms just described occurs, the read latency counter according to the prior art in accordance with FIG. 3a switches a very high-frequency clock signal that is present one counting clock too late and the S-DRAM outputs the data incorrectly too late. This in turn leads to considerable malfunctions of the whole system, in particular of the microprocessor connected to the S-DRAM.
FIG. 3b shows the write latency generator according to the prior art which is contained in the data path of the conventional S-DRAM. The conventional write latency generator illustrated in FIG. 3b receives an internal data path control signal (PAW) from the sequence controller. A synchronization circuit, which merely comprises a synchronization latch A, synchronizes the internal data path control signal to the VE clock signal. Said clock signal VE-CLK is completely synchronous with the external clock signal CLK-external. The internal data path control signal synchronized in this way is applied to a chain of series-connected time switching elements which each cause a time delay of one clock cycle. The time switching elements are clocked by the clock signal VE-CLK. Each of the time switching elements effects a signal time delay which is identical to the cycle time of the xcex94tcycle of the external clock signal.
In the case of the write latency generator according to the prior art as illustrated in FIG. 3b, the CAS latency is stored in the mode register, in which case, by way of example, a CAS latency of 6, a CAS latency of 5 and a CAS latency of 4 can be stored in the mode register. There are also memories with other latencies, such as, for instance, 2, 3 or 7.
The read latency or CAS latency specifies a number of clock cycles between the application of the external read command and the appearance of the output data at the OCD driver. Read latency CAS is understood to be the number of clock cycles which elapses before, after the application of a read command to a synchronous memory, the requested data appear at the output of the memory. A low read latency CAS has the advantage that a connected controller requires fewer waiting cycles. Depending on the length of internal signal propagation times, decoding times, amplifier propagation times on the memory chip, a low read latency CAS can be achieved, or higher read latencies have to be accepted. An important influencing factor in this case is the quality of the production process. However, these process fluctuations not only determine the read latencies CAS of the memory chip, but are also a main influencing factor for the ability of the memory chip to achieve high clock rates.
Write latency is understood to be the number of clock cycles which elapses between the application of a write command and the application of the data at the inputs of the memory chip. In conventional S-DRAMs, the read latency CAS can be programmed into a mode register. In the DDR2 standard, the write latency is coupled to the read latency CAS and amounts to one clock cycle fewer than the read latency.
Write latency=read latencyxe2x88x921.
As can be discerned from FIG. 3b, a CAS latency of 4 corresponds to a write latency of 3 and a time delay of 2xcex94tcycle by two timing elements of the write latency generator.
FIG. 4b shows a write operation in an S-DRAM given a stored CAS latency of 4. During the clock cycle 0 of the external clock signal, a write command WRITE is applied and decoded. The sequence controller generates an internal timing control signal which is generated with a certain signal delay, namely with the out-decoding time xcex94tDEK. This out-decoding time comprises a signal delay on account of the clock signal receiver, the clock signal line tree, the command decoding and on account of signal delays within the sequence controller. As the clock frequency of the external clock signal increases, the cycle time tcycle of the clock signal decreases. Since the time delay xcex94tDEK is constant, the situation arises, in the case of a clock signal at a very high frequency, in which the signal propagation time delay xcex94tDEK is greater than the cycle time tcycle. In this case, the PAW control signal can no longer be received with the signal edge 1 of the VE-CLK illustrated in FIG. 4b, but rather only with the signal edge 2 of the VE-CLK clock signal. The consequence of this is that the synchronization of the internal write signal PAW to PAWxe2x80x2 by the synchronizing circuit within the write latency generator is effected incorrectly one whole signal clock cycle later, i.e. with the signal clock cycle 2 instead of with the signal clock cycle 1. Consequently, if the clock cycle time falls into the time region of the out-decoding time on account of an excessively high clock frequency, a stable switch-on of the write data path within the S-DRAM is no longer ensured.
In order to avoid the above-demonstrated malfunction of the write latency circuit according to the prior art, it has been attempted hitherto to minimize the signal propagation times in order to reduce the delay time xcex94tDEK. In the same way, in the prior art it is attempted to minimize the decoding time tDEK by optimizing the propagation and decoding times to an extent such that it remains below the time tcycle.
In the case of reading, there is also the second error mechanism in which the offset of VECLK and DLCLK becomes greater than tcvc. This has been solved in the prior art by optimizing the time (tOCD+tFIFO).
At very high clock frequencies, however, the minimization of the signal propagation times encounters its limits or is insufficient to prevent a malfunction.
The read latencies (CAS) depend on the quality of the production process. In this case, process fluctuations determine not only the read latency of the memory chip, but also the ability of the memory chip to operate at high clock frequencies. Therefore, all memory chips are classified into so-called speed classes after production.
FIG. 5 shows such a speed class table according to the prior art. Memory cells which are sorted into a high speed class are able to operate at a very high operating clock frequency. Such high-frequency clock frequencies mean short clock cycle times. These short clock cycle times make it impossible, however, for such memory chips to ensure a low read latency, since the internal signal delay times are likewise somewhat shorter on account of the production process, but the absolute signal delay time is less favorable in relation to the clock cycle time. In the case of very high operating clock frequencies (tCLK) and thus very short clock cycle times (tCLK), the signal delay times come into the region of the clock cycle time or even fall below the latter.
The table shown in FIG. 5 shows, by way of example, the speed class division for a high-performance graphics memory. In the example illustrated in FIG. 5, three different CAS latencies can be programmed into the mode register. At a CAS latency of 6, the maximum permissible operating clock frequency is 455 MHz and the associated clock cycle time is 2.2 ns. At a CAS latency of 4, the maximum clock frequency is 333 MHZ and the associated clock cycle time is 3 ns. The shorter the CAS read latency, the lower the permissible operating clock frequency and the greater the corresponding clock cycle time must be in order to avoid malfunctions.
The object of the present invention is to provide a control circuit for a data path of an S-DRAM which ensures a reliable functioning of the data path even in the case of a clock signal at a very high frequency.
This object is achieved according to the invention by means of a control circuit. The invention provides the control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, the control circuit according to the invention being distinguished by the fact that provision is made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific, delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.
In this case, an associated signal delay element is preferably provided for every possible stored latency value.
The data path control signal is preferably switched through without any delay if the stored latency value is low.
The maximum permissible clock signal frequency of the clock signal for the S-DRAM preferably rises as the latency value increases.
The minimum permissible cycle time of the clock signal for the S-DRAM preferably decreases as the latency value increases.
The delay time of the delay element preferably lies between a minimum delay time (Delaymin) and a maximum delay time (Delaymax), the minimum delay time (Delaymin) being equal to the difference between the largest permissible cycle time and a control signal propagation time delay (TDEK) of the data path control signal, and the maximum delay time (Delaymax) being equal to the difference between twice the minimum permissible cycle time and the control signal propagation time delay (TDEK)of the data path control signal.
The signal delay elements are preferably connected in parallel to inputs of the first multiplexer, which receives a first control signal by means of the latency decoder.
The data path control signal is preferably a data enable control signal for a latency generator of the data path.
The latency generator is preferably a read latency generator or a write latency generator.
Preferably, the controllable latency generator has a plurality of series-connected time switching elements which in each case switch through a signal present at a signal input, each with the cycle time of the clock signal, with a time delay to their respective signal output.
In this case, the signal outputs of the time switching elements are preferably in each case connected to a signal input of a controllable second multiplexer within the latency generator.
The second multiplexer preferably has a control input for a second control signal output by the latency decoder.
The signal delay of all the series-connected time switching elements is preferably equal to a maximum programmable latency (CAS) minus two cycle times.
The latency decoder preferably drives the second multiplexer in the event of a low stored latency in such a way that the signal delay effected by the time switching elements is equal to the stored latency minus two clock cycle times, and the latency decoder drives the second multiplexer in the event of a high stored latency value in such a way that the signal delay effected by the time switching elements is equal to the stored latency reduced by a further cycle time.
In a preferred embodiment, the latency generator has a synchronization circuit for synchronizing the data path control signal to a clock signal which is synchronous with the external clock signal.
Preferred embodiments of the control circuit according to the invention are described below with reference to the accompanying figures in order to elucidate features that are essential to the invention.